Method of manufacture of raised source drain mosfet with top notched gate structure filled with dielectric plug in and device manufactured thereby

ABSTRACT

A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A plug of dielectric material is formed in a notch in a cap layer above the gate polysilicon. The sidewalls of the gate electrode is covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

BACKGROUND OF INVENTION

This invention relates to methods of manufacture of FET semiconductordevice, and more particularly to methods of manufacture of SOI CMOSstructures and devices manufactured thereby.

Scaling (reduction in dimensions) of Silicon-On-Insulator (SOI)Complementary Metal Oxide Semiconductor (CMOS) structures requiresscaling of the silicon thickness to achieve device performance targets(short channel control, etc.).

FIG. 1A shows the typical structure of a prior art SOI device 10 priorto epitaxial growth of the raised source/drain regions 28S/28D of FIG.1B on the surface of the thin silicon layer 12 of the device 10. Thedevice 10 includes a thin silicon layer 12 formed on a Buried OXide(BOX) layer 12. A gate electrode stack formed of dielectric (gate oxide)layer 14 upon is formed above the thin silicon layer 14, a gateelectrode 18 composed of polysilicon formed above the gate dielectriclayer 14, and a hard mask 22 above the gate electrode 18 has beenformed. Sidewall spacers 16 composed of silicon oxide have been formedon the sidewalls of the gate electrode 18 and are intended to cover thesidewall surfaces of the of the gate electrode 18 entirely.

Note the pull-down of the spacers 16 below the hard mask 22 resulting inexposure of some of the sidewall surfaces of the polysilicon at the topcorners of the gate electrode 18. This is typical of the spacerpull-down due to normal processing (spacer overetch, etc.). Reduction ofthis pull-down by means known heretofore would tend to reduce therobustness of the overall process (residual nitride, etc).

FIG. 1B shows the device 10 of FIG. 1A after growth of the raised source28S and the raised drain 28D on the surface of the thin silicon layer12. The problem which is illustrated by FIG. 1B is that the exposure ofthe upper corners of the gate electrode 18 has led to spurious growth ofsilicon nodules 28T is seen in the region exposed at the top corners ofthe gate electrode 18.

The process requirement in the past has been to protect the polysiliconof the gate polysilicon 18 with spacers 16 for the purpose of avoidingthe formation of spurious epitaxial growth during the raised sourcedrain formation.

Silicidation is the process of converting a Silicon (Si) material to asilicide material. As a result of the silicidation process, theconsumption of silicon thereby depends on the type of silicide beingformed. For example, formation of cobalt silicide (CoSi) consumes moresilicon than formation of nickel silicide (NiSi). Raised source anddrain structures are required in SOI CMOS because the silicon layer inwhich the device is formed is reduced in thickness. This is the primaryenabling element, i.e. strategy, for achieving continued reduction insilicon thickness.

The process of formation of raised source/drain regions suffers from avery limited process window. Any exposure of the gate polysiliconthrough either the hard mask 22 and/or above the sidewall spacers 16results in unwanted epitaxial growth of silicon nodules 28T on the uppersurfaces of the gate electrode 18 where they are exposed.

SUMMARY OF INVENTION

An object of this invention is to provide a method/process for forming astructure which eliminates the propensity for exposure of gatepolysilicon.

Another object of this invention is to provide such a structure.

In accordance with this invention, a method is provided for forming anSOI MOSFET device with a silicon layer formed on a dielectric layer witha gate electrode stack, with sidewall spacers on sidewalls of the gateelectrode stack and raised source/drain regions formed on the surface ofthe silicon layer. The gate electrode stack comprises a gate electrodeformed of polysilicon above a gate dielectric layer, which is formed onthe surface of the silicon layer. A cap comprising an amorphous siliconlayer is formed on the top surface of the gate polysilicon. A notch isformed in the periphery of the cap layer. The notch is filled with aplug composed of a dielectric material. The plug formed in the notchextends down below the level of the top of the sidewall spacers for thepurpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raisedsource/drain regions is avoided.

BRIEF DESCRIPTION OF DRAWINGS

The foregoing and other aspects and advantages of this invention areexplained and described below with reference to the accompanyingdrawings, in which:

FIG. 1A shows the typical structure of a prior art SOI CMOS FET devicebefore formation of raised source/drain regions of FIG. 1B on thesurface of the thin silicon layer of the device.

FIG. 1B shows the device 10 of FIG. 1A after growth of the raised sourceand the raised drain by epitaxial growth of silicon on the surface ofthe thin silicon layer with spurious growth of unwanted nodules at theupper corners of the gate electrode formed during the process ofepitaxial growth.

FIG. 2A shows the device of FIG. 1A, which has been modified inaccordance with this invention by forming an amorphous silicon layer onthe upper surface of the gate electrode prior to forming the hard maskon the top surface of the gate electrode, above the amorphous siliconlayer.

FIG. 2B shows the device of FIG. 2A after raised source/drain formationwith the improvement that the epitaxial growth is on the source anddrain only without formation of any nodules of epitaxial silicon on thetop corners of the gate polysilicon.

FIGS. 3A-3J illustrate the process flow in accordance with thisinvention for constructing the device of FIGS. 2A and 2B.

FIG. 4 is a process flow chart of the etching steps used as illustratedby FIGS. 3E to 3G to selectively undercut the selectively amorphizedlayer at the top of the blanket polysilicon layer and then to etch thegate polysilicon and gate dielectric to form the gate electrode.

DETAILED DESCRIPTION

Referring to FIGS. 2A and 2B, this invention provides a method fordefining a raised source region 28S and a raised drain region 28Dself-aligned with the gate electrode 18 and its sidewall spacers with agood process window. In particular, this invention provides amethod/process for forming the structure of FIG. 1B without the growthof the spurious nodules 28T by protecting against the exposure of thepolysilicon of the sidewalls of the gate electrode 18 to the epitaxialdeposition process, which forms the raised source/drain regions 28S/28D.

The process requirement of the method of this invention is to insert anadditional layer of dielectric material between the gate polysilicon 18and the spacers 26S for the purpose of eliminating the exposedpolysilicon of the gate polysilicon 18 and avoiding the formation ofspurious epitaxial growth during the formation of raised source/drainregions 28S/28D.

FIG. 2A shows the device 10 of FIG. 1A, which has been modified inaccordance with this invention by forming an amorphous silicon layer 21Bon the upper surface of the gate electrode 18 prior to forming the hardmask 22 on the top surface of the gate electrode 18, above the amorphoussilicon layer. Then notches 24 (shown in FIGS. 3F and 3G) were formed atthe top of the gate electrode 18 by etching away the outer edges of theamorphous silicon layer 21B. The notches 24 at the top of the gateelectrode 18 were filled with dielectric plugs 26P thereby forming a TopNotched Gate (TNG) structure. The notches 24 were filled with thedielectric plug 26P to prevent formation of the kinds of nodules 28Tseen in FIG. 1B on the polysilicon at the upper end of the gateelectrode 18.

FIGS. 2A and 2B are analogous to FIGS. 1A and 1B, showing the structurebefore and after the formation epitaxial raised source/drain regions28S/28D.

FIG. 2A shows spacer pull down to the same level as FIG. 1A, but thedielectric plug 26P prevents exposure of the polysilicon of the gateelectrode 18 during the step of forming the raised source/drain regions28S/28D.

FIG. 2B shows the device 10 of FIG. 2A after formation of the raisedsource/drain regions 28S/28D with the improvement that the epitaxialgrowth is only at the site of the source region 28S and drain regions28D. There is no spurious growth on the top corner of the polysilicon ofthe gate electrode 18 of the kind seen in FIG. 1B.

FIGS. 3A-3J illustrate the process flow to construct the structure ofFIGS. 2A and 2B. One advantage of this method/structure of thisinvention is that there is very little processing required above thenormal process flow. The key is to form a top notched gate structure(TNG) with notches 24 which can then be filled with a set of dielectricplugs 26P during the normal process flow. The structure is formed usingthe following steps.

Preparation for the selective undercut of a thin region at the top ofthe gate polysilicon must be done in a controlled and repeatable mannerby forming an amorphous layer on the surface of the polysilicon layerwhich is to be formed into a gate electrode.

FIG. 3A shows a potential gate electrode stack comprising SOI materialBuried OXide (BOX) layer 11 of silicon dioxide covered with aconventional SOI thin silicon layer 12. A blanket layer of gate oxidelayer 14B and a blanket polysilicon layer 18B have been formed over theBOX layer 11. The polysilicon layer 18B may be doped or undoped.

FIG. 3B shows the stack of FIG. 3A after the first step of the presentinvention leading to the formation of the TNG structure of thisinvention, which is to form a blanket, thin amorphous silicon layer 21Bon the top surface of the polysilicon layer 18B in the process of ionimplantation into the top surface of the blanket polysilicon layer 18for the gate electrode 18. Germanium or silicon ions (21I) are implantedto a dose sufficient to amorphize the desired thickness of polysilicon.The thickness of the amorphous layer can be tailored by the choice ofion energy used.

FIG. 3C shows a process of gate patterning applied to the device 10 ofFIG. 3B. This is done starting with the deposition over the surface ofthe blanket amorphous silicon layer 21B of a blanket hard mask layer 22Bcomposed of a hard mask material (e.g. silicon nitride, TEOS, etc) andthen proceeding with the initial steps of photolithographic patterningby forming a photoresist (PR) mask 23 over the blanket hard mask layer22B.

FIG. 3D shows the device 10 of FIG. 3C after the photoresist mask 23 hasbeen used during etching of the hard mask layer 22B into the pattern ofthe photoresist mask 23, by hard mask Reactive Ion Etching (RIE) to forma hard mask 22 adapted for patterning the gate electrode stack.

FIG. 3E shows the device 10 of FIG. 3D after stripping of the PR mask 23from the patterned hard mask 22.

FIG. 3F shows the device 10 of FIG. 3E after the TNG selective formationof the notches 24 in the amorphous silicon layer 21B of FIG. 3E asundercut notches 24 below the hard mask 22 to form amorphous silicon cap21 between the notches 24. Selective undercut of the amorphized layer21B to form amorphous silicon cap 21 is done during polysilicon RIE(described in detail below).

FIG. 3G shows the device of FIG. 3F, with the TNG structure afteretching of the blanket polysilicon layer 18B and the blanket gatedielectric layer 14B by RIE to form the polysilicon gate electrode 18and gate dielectric layer 14 aligned with hard mask 22. This is donewith a standard RIE etch for selectively etching polysilicon withrespect to the hard mask 22

FIG. 3H shows the device 10 of FIG. 3G after blanket deposition of aspacer layer 26B composed of an appropriate spacer material covering thesurface of device 10 while at the same time it is filling the notches 24in the amorphous silicon layer 21B with material which will provide theplugs 26B seen in FIGS. 2A and 2B. The spacer material in the spacerlayer 26B is composed of any spacer material such as dielectricmaterial, e.g. silicon oxide or silicon nitride.

FIG. 3I shows the device 10 after etching back the spacer layer 26B toform spacers 26S on the sidewalls of the gate electrode 18 at the sametime as plugs 26P are being formed in the undercut notches 24 at the topof the gate structure, to provide for protection of the polysilicon ofthe gate electrode 18 during the subsequent epitaxial raised sourcedrain formation shown by FIG. 3J.

FIG. 3J shows the device of FIG. 3I after formation of the raisedsource/drain regions 28S/28D juxtaposed with the sidewall spacers 26Swith no nodules formed at the top of the gate electrode 18 during theepitaxial process used to form raised source/drain regions 28S/28D.

At this point the polysilicon sidewall spacers 26S and top cap 22 can beremoved and conventional process steps, as known to those skilled in theart, can be applied to finish the formation of the FET structure.

Formation of Undercut

Referring again to FIG. 3E, the etching step used to selectivelyundercut the selectively amorphized layer 21B at the top of the blanketpolysilicon layer 18B, as well as complete the gate polysilicon etch,will now be described with reference to FIG. 4. The polysilicon etch canbe adjusted to produce a precision undercut at the top of the gate layer18B. This is accomplished by using a three step etching process. Thisetching process which starts at 40 in FIG. 4 is performed in a decoupledplasma etch reactor (not shown).

Formation of Top Notch/Undercut.

In step 42, the initial breakthrough and etching of theamorphized/predoped polysilicon layer 21B is performed. This processstep uses a low pressure (4-6 mT) and high bias etch (180-200 W) with80-120 HBr (hydrogen bromide) and a small amount of oxygen (O_(2,) 2-10sccm). This step produces the notches 24 by undercutting the amorphoussilicon layer 21B. Further, the amount of the undercut of layer 21B isvery precisely controlled by the HBr/O₂ ratio.

Passivation of Top Notch/Undercut For Precision TNG Control.

In step 44, a passivation step is performed in which sidewalls of notch24 must be passivated to maintain the notch during remainder of gateetch. This step grows a silicon oxide layer (not shown) that is thickeron the exposed surface of the implant damaged/predoped amorphous siliconlayer 21B. This step uses a pressure in the range of 40-60 mT, high topsource power (450-650 W) with pure oxygen (O₂, 100-150 sccm).

Horizontal Passivation Breakthrough Etch And Etching to Form thePolysilicon Gate Electrode and the Gate Dielectric Layer.

In step 46, a short breakthrough step is performed, followed by etchingof the remaining polysilicon/gate dielectric stack, i.e. layers 18B/14B.The polysilicon and gate dielectric etch is a highly selectivity RIEprocess using materials such as HBr, Oxygen (O₂) and Helium (He) in theprocess. This process step uses a pressure range of 20-60 mT andtop/bottom power of 200-400 W and 30-100 W respectively with HBr(150-300 sccm), 0 (4-10 sccm) and He as the diluent gas. This is astandard gate polysilicon/gate dielectric etch step.

The formation of the undercut and the polysilicon/gate dielectricetching process ends at step 48, with the device 10 being removed fromthe decoupled plasma etch reactor.

While this invention has been described in terms of the above specificembodiment(s), those skilled in the art will recognize that theinvention can be practiced with modifications within the spirit andscope of the appended claims, i.e. that changes can be made in form anddetail, without departing from the spirit and scope of the invention.Accordingly all such changes come within the purview of the presentinvention and the invention encompasses the subject matter of the claimswhich follow.

1. A method of forming an SOI MOSFET device with a silicon layer formedon a dielectric layer with a gate electrode stack, with sidewall spacerson sidewalls of the gate electrode stack and raised source/drain regionsformed on the surface of the silicon layer, wherein the gate electrodestack comprises a gate electrode formed of polysilicon over a gatedielectric layer formed on the surface of the silicon layer, comprisingthe steps of: forming a cap layer over the gate electrode layer, forminga gate mask for patterning the gate electrode over said polysilicon,said mask covering a portion of said cap layer, and said mask having apattern and having a periphery, etching the cap layer in the pattern ofthe gate mask with the etching process undercutting below said cap layerunder the periphery of the mask thereby forming a notch in the cap layerbelow the mask, patterning the electrode stack by etching in saidpattern of said gate mask, filling the notch with dielectric plugsbetween the gate polysilicon and the sidewall spacers for the purpose ofeliminating the exposure of the gate polysilicon, forming said sidewallspacers reaching along the sidewalls of the gate electrode to above thelevel where said plugs contact the gate polysilicon, and forming araised source region and a raised drain region on top of said siliconlayer aside from said spacers, whereby formation of spurious epitaxialgrowth during the formation of raised source/drain regions is avoided.2. The method of claim 1 wherein the cap layer comprises amorphoussilicon formed by ion implantation of the polysilicon prior to formingthe gate mask.
 3. The method of claim 1 wherein said dielectric plugsand said sidewall spacers are formed by forming a blanket layer of adielectric material which is etched back to form said plugs and saidsidewall spacers.
 4. The method of claim 2 wherein said dielectric plugsand said sidewall spacers are formed by forming a blanket layer of adielectric material which is etched back to form said plugs and saidsidewall spacers.
 5. The method of claim 1 wherein said gate maskcomprises a hard mask, and said cap layer comprises amorphous siliconformed by ion implantation of the polysilicon prior to forming the gatemask.
 6. The method of claim 1 wherein said gate mask comprises a hardmask, and said dielectric plugs and said sidewall spacers are formed byforming a blanket layer of a dielectric material which is etched back toform said plugs and said sidewall spacers.
 7. The method of claim 6wherein said dielectric plugs and said sidewall spacers are formed byforming a blanket layer of a dielectric material which is etched back toform said plugs and said sidewall spacers.
 8. The method of claim 1wherein said cap layer is etched in the pattern of the mask. with a lowpressure high bias etch forming said notch by said undercutting belowsaid cap layer.
 9. The method of claim 1 wherein said cap layer isetched in the pattern of the mask. with a low pressure high bias etchforming said notch by said undercutting below said cap, and then exposedsurfaces of said cap layer are passivated by growing silicon oxidethereon.
 10. The method of claim 1 wherein said cap layer is etched inthe pattern of the mask. with a low pressure high bias etch forming saidnotch by said undercutting below said cap, then exposed surfaces of saidcap layer are passivated by growing silicon oxide thereon, and then saidpolysilicon and said gate dielectric are etched in a highly selectiveRTE process in the pattern of said mask.
 11. A method of forming an SOIMOSFET device with a silicon layer formed on a dielectric layer with agate electrode stack, with sidewall spacers on sidewalls of the gateelectrode stack and raised source/drain regions formed on the surface ofthe silicon layer, wherein the gate electrode stack comprises a gateelectrode formed of polysilicon over a gate dielectric layer formed onthe surface of the silicon layer, comprising the steps of: forming a caplayer composed of amorphous silicon over the gate electrode layer,forming a gate mask for patterning the gate electrode over saidpolysilicon, said mask covering a portion of said cap layer, and saidmask having a pattern and having a periphery, etching the cap layer inthe pattern of the gate mask with the etching process undercutting belowsaid cap layer under the periphery of the mask thereby forming a notchin the cap layer below the mask, patterning the electrode stack byetching in said pattern of said gate mask, filling the notch withdielectric plugs between the gate polysilicon and the sidewall spacersfor the purpose of eliminating the exposure of the gate polysilicon,forming said sidewall spacers reaching along the sidewalls of the gateelectrode to above the level where said plugs contact the gatepolysilicon, and forming a raised source region and a raised drainregion on top of said silicon layer aside from said spacers, wherebyformation of spurious epitaxial growth during the formation of raisedsource/drain regions is avoided.
 12. The method of claim 11 wherein theamorphous silicon of said cap layer is formed by ion implantation of thepolysilicon prior to forming the gate mask.
 13. The method of claim 11wherein said dielectric plugs and said sidewall spacers are formed byforming a blanket layer of a dielectric material which is etched back toform said plugs and said sidewall spacers.
 14. The method of claim 12wherein said dielectric plugs and said sidewall spacers are formed byforming a blanket layer of a dielectric material which is etched back toform said plugs and said sidewall spacers.
 15. The method of claim 11wherein said gate mask comprises a hard mask, and said cap layercomprises amorphous silicon formed by ion implantation of thepolysilicon prior to forming the gate mask.
 16. The method of claim 11wherein said gate mask comprises a hard mask, and said dielectric plugsand said sidewall spacers are formed by forming a blanket layer of adielectric material which is etched back to form said plugs and saidsidewall spacers.
 17. The method of claim 16 wherein said dielectricplugs and said sidewall spacers are formed by forming a blanket layer ofa dielectric material which is etched back to form said plugs and saidsidewall spacers.
 18. The method of claim 11 wherein said cap layer isetched in the pattern of the mask. with a low pressure high bias etchforming said notch by said undercutting below said cap layer.
 19. Themethod of claim 11 wherein said cap layer is etched in the pattern ofthe mask. with a low pressure high bias etch forming said notch by saidundercutting below said cap, and then exposed surfaces of said cap layerare passivated by growing silicon oxide thereon.
 20. A SOI MOSFET devicewith a silicon layer formed on a dielectric layer with a gate electrodestack, with sidewall spacers on sidewalls of the gate electrode stackand raised source/drain regions formed on the surface of the siliconlayer, wherein the gate electrode stack comprises a gate electrodeformed of polysilicon over a gate dielectric layer formed on the surfaceof the silicon layer, comprising the steps of: cap layer over the gateelectrode layer, a gate mask for patterning the gate electrode over saidpolysilicon, said mask covering a portion of said cap layer, and saidmask having a pattern and having a periphery, the cap layer being in thepattern of the gate mask with an undercut below said cap layer under theperiphery of the mask in the form of a notch in the cap layer below themask, the notch being filled with dielectric plugs between the gatepolysilicon and the sidewall spacers for the purpose of eliminating theexposure of the gate polysilicon, said sidewall spacers reaching alongthe sidewalls of the gate electrode to above the level where said plugscontact the gate polysilicon, and a raised source region and a raiseddrain region on top of said silicon layer aside from said spacers.